The present invention relates generally to the specifically directed plating of indium and tin bronzes on copper structures, and particularly, but not by way of limitation, to coating the top surface of semiconductor interconnects with an indium, or tin bronze or an oxide thereof. The invention also relates to the interconnect so formed.
It is desirable to selectively cap copper interconnects with an alloy coating to provide improved adhesion, electromigration resistance, redundant current-strapping, improved via contact resistance, robustness, and corrosion protection. The capping must be highly selective, specifically plating only the copper wiring, so as not to require expensive and critical lithography and etching to define the cap over the interconnect and to remove it from the spaces between interconnects. Cu on-chip contacts (e.g. wire bond or C4 pads) need similar capping for robust, corrosion-resistant terminal metallurgical contact. Previously, this problem has been addressed by electroless or alloy-formed selective capping (e.g. by electroless CoP/Au, NiP/Au, or PVD-deposited In or Sn with alloying reactions to the Cu) followed by selective wet-etching. These solutions are subject to shorting across very finely-spaced interconnects. A selective process which solves this problem is the immersion (autocatalytic exchange) replacement of Cu surface atoms with Sn or other species. The Cu/Sn/O system is resistant to oxidation only to xcx9c300xc2x0 C. The Cu/In/O system of the invention is more highly resistant, with stability extending to temperatures in excess of 400xc2x0 C.
In immersion (or chemical displacement) coating, the substrate, usually a metal, is coated with a film (usually metallic) from a solution that contains the coating material in ionic form. The immersion coating process does not require a separate reducing agent as in electroless or auto catalytic deposition, or electric current as in electroplating. Rather, the substrate metal acts as the reducing agent, for example as when iron (Fe) is immersed in a copper sulfate solution:
Cu2++Fexe2x86x92Cu+Fe2+
Here, Fe supplies electrons to the Cu ions, reducing them to zerovalent Cu, which coats the Fe substrate. The resultant Fe2+ ions dissolve into solution. The deposition of Cu and Fe is straightforward in that the standard electrochemical potential for Cu/Cu2+ couple (0.34 V vs. the normal hydrogen electrode) is greater than that of the Fe/Fe2+ (xe2x88x920.44 V vs. the normal hydrogen electrode); since Cu is more xe2x80x9cnoblexe2x80x9d, or thermodynamically xe2x80x9cinertxe2x80x9d with respect to Fe, it may be said to have a greater driving force than Fe for residing in an zerovalent state. Thus, when uncomplexed Cu2+ ions encounter Fe metal, the Cu2+ ions spontaneously oxidize the Fe to Fe2+ forming zerovalent Cu, which remains on the Fe surface as a film.
The deposit thickness obtained by immersion coating is limited, since the coating metal covers the base substrate, thereby preventing access of the coating ions in solution (Cu2+ ions in solution), and removal of the base substrate product ions (Fe2+ in our example). Typically, coating thicknesses are in the range of 10-1000 mm.
Relatively few metals can be deposited by an immersion process, mainly because of standard potential mismatch. A well-known example is immersion deposition of tin on copper (e.g., U.S. Pat. No. 2,282,511). However, the standard potential of Sn/Sn2+ (xe2x88x920.137 V vs. the normal hydrogen electrode, NHE) is less than either the Cu/Cu2+ (0.34 V vs. NHE) or the Cu/Cu+ (0.51 V), indicating that Cu would tend to immersion deposit on Sn, but not Sn on Cu. Nevertheless bat complexing the Cu+ ions in solution with a complexant such as cyanide or thiourea (often known as thiocarbamide), one can lower the standard potential of the Cu/Cu+ couple below that of Sn/Sn2+. Thus, Sn now has a spontaneous tendency to immersion deposit on Cu.
The standard potential of the In/In3+ couple is xe2x88x920.34 V(NHE), and xe2x88x920.126 V (NHE) for In/In+. However, the only stable In ion in aqueous solutions is In3+. The In/In3+ couple potential (xe2x88x920.34 V (NHE)) is ca. 0.2 V more negative than the of Sn/Sn2+ (xe2x88x920.137 V (NHE)), which indicates that In should be more difficult than Sn to deposit on Cu by an immersion process from solution. Immersion and/or electroless plating baths are known in the art. Bokisa et al. (U.S. Pat. No. 5,554,211) describe one such bath that differs from the present invention in that it specifically does not contain thiourea and whereas the bath of the present invention contains sulfuric acid, Bokissa et al. recite the use of fluoboric and alkane or alkanol sulfonic acids. Sricharoenchaikit et al. (U.S. Pat. No. 5,203,911) specifically require the use of low metal ion concentrations from 1 to 10 millimolar, whereas the present invention operates in the range of from about 65 to about 200 millimolar. The reference specifically recites the disadvantages of hypophosphite and alkali metals, both of which are recited in the present invention. The chemical displacement solution of King et al. (U.S. Pat. No. 5,217,751) requires, in addition to an ionic solution of the plating metal, the presence of a source of the free metal in contact with the solution. This is a disadvantage not present in the present invention. Holtzman et al. (U.S. Pat. No. 4,715,894) describe a chemical displacement composition suitable for the deposition of a layer of tin or indium. The plating solution of Senda et al. (U.S. Pat. No. 5,364,459) requires titanium salts many of which are regulated by the Toxic Substances Control Act and are likely to present disposal issues. However, each of these described systems is limited to plating a layer of metal. The problem of plating a layer of alloy was not addressed by the prior art.
As the standard and best known method for fabricating Cu interconnects is the Damascene or dual-Damascene process with electroplated Cu fill, this leaves Cu interconnects encapsulated on three sides with a refractory liner, but exposed on the top surfaces after chemical-mechanical planarization. If the top surface could also be capped with a highly adhesive, corrosion-resistant metal, then reliability would be improved, and as well there would be more freedom in the choices for subsequent processing steps, which might attack or corrode exposed Cu and could not be used in the uncapped case. It is thus desirable to selectively cap Cu interconnects with indium or tin bronze or oxides and to provide a method of controllably and selectively depositing the In or Sn bronze in very thin layers only on the exposed surfaces of Cu interconnects. Such undesired coating on the insulating surfaces between the interconnects would lead to unwanted electrical shorts. To eliminate these shorts, either an additional masking step and etching, or a selective etching step without masking would be required to removed this undesired In or Sn coating.
Due to the existence and commercial availability of an immersion Sn plating bath for Cu, the immersion-plated Cu/Sn/Au ternary system is known, and was studied here specifically for the new application of terminal wire bond metallurgy on Cu interconnects. The Au is necessary to prevent native Sn oxides from preventing good wire bonding by the thermal/ultrasonic ball-bonding or wedge-bonding techniques. The Cuxe2x80x94Snxe2x80x94Au ternary compound layer has been investigated as a protective layer covering Cu interconnects for wire bonding, and for probe damage resistance, oxidation resistance, and as a Cu diffusion barrier. The proposed compound layer is formed by selective immersion Sn coating on Cu terminal pads formed by the Damascene process during the normal course of Cu interconnect fabrication, followed by immersion (and/or electroless) Au coating and appropriate annealing steps. RBS analysis has been used to follow the reaction products of the ternary system. The initial thickness of Sn and Au layers investigated ranges from a few tens to a few thousands of angstroms. Gold wire bonding evaluation on the Auxe2x80x94Snxe2x80x94Cu ternary was promising. A diffusion barrier experiment performed at 400xc2x0 C., in forming gas did also yield an encouraging result. However, RBS (FIG. 4) and Auger (FIG. 5) data after subsequent aggressive corrosion stressing indicated that the system allows Cu penetration through the alloy and Sn oxide to the surface, for sustained temperatures above approximately 300-350xc2x0 C. This result is consistent with published studies (D. N. Wang, A. C. Miller, and M. R. Notis, xe2x80x9cXPS Study of the Oxidation Behavior of the Cu3Sn Intermetallic Compound at Low Temperaturesxe2x80x9d Surface and Interface Analysis, 24, 127 (1996)) of Cu(Sn) alloy thin films. Thus the Cu(Sn, O) system may be applicable for many types of chips or packages with Cu thin film wiring, but might be unsuitable for capping Cu interconnects in the more aggressive processing technologies, where temperature cycling to approximately 400xc2x0 C. is routinely employed during the fabrication process.
A method is provided for forming a coating of indium or tin on copper or aluminum substrates and in particular the method provides that the indium or tin is deposited on the copper surfaces and not silicon or insulator surfaces.
The invention also provides layers of indium or tin bronzes as barriers to the electromigration of copper. The method also attains oxides of those bronzes that act to prevent uncontrolled growth of copper corrosion products.
In one embodiment of the invention a copper substrate having at least one exposed Cu surface is immersed in a deposition bath containing the ionic form of a plating metal. According to aspects of the invention, the ion, In3+, or Sn2+, is chelated by a complexing agent such as thiourea. When the copper substrate is immersed, a selective autocatalytic process commences whereby an indium or tin coating is grown on the copper substrate. According to some aspects of the invention, the thickness of the film is controlled by the autocatalytic nature of the process to be no thicker than about 1000 angstroms, in other embodiments, lesser thicknesses are achieved by control of the immersion time. Subsequent annealing in an inert or reducing ambient, or in an oxidizing ambient, respectively forms Cu alloys (i.e., bronzes) and oxides.
According to some embodiments of the invention, the copper substrate is a Cu-damascene (or dual damascene) interconnect, fabricated through the CMP planarization step, leaving an exposed upper surface. In other embodiments, the interconnect is formed such that top and side surfaces are exposed. In further embodiments of the invention, the copper substrate is a Cu on chip contact, such as a wire bond pad or a C4 pad.
The invention further provides autocatalytic baths, and compositions therefore, useful for the electroless plating of indium or tin on exposed copper or aluminum surfaces.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Specifically, the invention is herein described in terms of the semiconductor field, but nothing inherent to the invention so limits it. It is understood that the invention will have application in various of the other arts. Moreover, the description is in terms of certain selected devices within the semiconductor arts, but the invention is not limited to such devices. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.